Foundry Sponsored, TSMC 55 LeFP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).

• Ultra High-Density
• 7% up to 15% denser after P&R than standard 7-Track library
• Hand tuned cells, designed with 6-Track for optimal area reduction
• Pulsed latches as ?Spinner Cells? instead of flip-flops: for min. 30% gain in density
• Metal 1 power rails
• With smooth implementation
• Pulse generation automated by the script for ?Insert pulse generation?
• Spinner cell design minimizing hold time violations
• Ideal for slow to medium speed logic blocks
• Flexibility and ease of integration
• Multi VTs (SVT, LVT and HVT MOS versions) to deliver optimal performance, power and area results
• Support of CCS timing and power
• Complete set of PVT corners including temperature inversion corners, multi VDD characterization, custom PVT support