Foundry sponsored - Two Port Register File compiler - TSMC 90 nm LPeF - Memory optimized for high density and low power optimized - compiler range up to 40 k
Key Benefits
- Reduce die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Routing allowed upwards from Metal 4, Support Metal 5 top Metal option
- Extend battery life
- Ultra low leakage thanks to careful design structures
- Optional byte write and bit wise write capability
- Data retention mode
- Make integration easier
- Wide flexibility for words and bits per word
- Two Read/Write Ports which implements Two-port
- Register File (1R/1W) functionality
- Enable right on-first-pass design
- Complete mismatch validation of the memory architecture taking in account local and global dispersion
- Extended validation for high coverage rate of the compiler
- Decrease of Time-To-Market
- Multi foundries support using the same architecture
Performances
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Variants
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VT Bit cell
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VT Periphery
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Operating Voltage
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Capacity
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Option mode
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90 LP eFlash
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HD HVT | HVT | Nominal voltage: 1.2 V +/-10% |
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