Key Benefits

  • Smart periphery design to reach the highest density
  • Up to 25% denser than traditional dual port memory compilers
  • Pushed rule bit cell from foundry
  • Power reduction features
  • Low power architecture even at nominal voltage: Up to 30% less consuming than standard memory compilers available at 65 nm LP
  • Optional Byte write (MUX 2 and 4) and bit-wise write capability (MUX 8)
  • Ultra low leakage design
  • Up to 40% less leaky in stand by mode compared with a standard offering at 65 nm LP
  • Data retention mode
  • Easy integration
  • MUX options
  • Data range flexibility allows easy addition of bits for redundancy or ECC purposes
  • Address range flexibility allows easy addition of single rows for redundancy purposes
  • Two completely independent Read/Write Ports which implements full Dual-Port (2RW) functionality or alternatively can be used as 2PRFile (1R/1W) or 2R/1W
  • The Dolphin quality
  • Complete mismatch validation of the memory architecture taking into account local and global dispersion
  • Optional BIST for industrial fabrication test of instances

Performances

Variants
VT Bit cell
VT Periphery
Operating Voltage
Capacity
Option mode
65 LP
HD SVT SVT Nominal voltage:
1.2 V +/-10%

64 bits to 40 kbits -