Amidst a rich a-la-carte offering, shCODlp-100.02 is an optimized and complete configuration around high performance DAC and ADC cores which provide a higher SNR for the smallest silicon area. Fabless companies targeting high fabrication volume would benefits from shCODlp-100.02 optimization for 0.11 um optically shrunk processes.

Key Benefits

  • Maximized yield with the best trade-off between silicon area and SoC / PCB costs
  • Capacitor-less headphone driver
  • Filter-less line-out
  • PLL-less feature to avoid jitter noise issues
  • Single master clock generates all sampling frequencies

Key Performances

  • SNR: 95 dB on ADC path and 100 dB on DAC path
  • Output power: 40 mW per channel at 3.3 V on 16 Ω
  • load for the headphone driver
  • Fs: From 8 to 96 kHz