Foundry Sponsored, TSMC 130 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).
- Foundry sponsored library
- Ultra High Density
- 10% up to 20% denser after P&R compared to standard 9-Track library
- Pulsed latches as Spinner Cells instead of D-flip flops: for min. 30% gain in density at cell level
- Metal layer 2 available for routing as only Metal 1 used for cell design
- 6-Track cells for optimal area reduction
- SVT MOS version is provided in foundry sponsored offering to minimize power consumption on timing relaxed paths
- LVT MOS and HVT MOS are provided as options
- Smooth implementation:
- Pulse generation automated by the script for ?Insert pulse generator?
- Spinner cell design minimizing hold time violations
- Optimal Design for Yield:
- Design methodology ensuring High-Yield circuits despite Mismatch
- Compliance with TSMC IP 9000 qualification process