Key Benefits

  • REACH HIGHEST DENSITY
  • Smart periphery design for significant gain in density
  • EXTEND BATTERY LIFE
  • Data retention mode at 1.2 V and 0.9 V to divide drastically the leakage compared to simple stand by mode
  • Byte write capability
  • MAKE INTEGRATION EASIER
  • Data range flexibility allows easy addition of bits for redundancy or ECC purposes
  • Address range flexibility allows easy addition of single rows for redundancy purposes
  • ENABLE RIGHT ON FIRST PASS DESIGN
  • Complete mismatch validation of the memory architecture taking in account local and global dispersion
  • Extended validation for high coverage rate of the compiler

Performances

Variants
VT Bit cell
VT Periphery
Operating Voltage
Capacity
Option mode
55 uLP eFlash
eHVT HVT
SVT
Nominal voltage:
1.2 V +/-10%

Low voltage:
0.9 V +/-10%

64b - 40960b -