Single Port Register File compiler - TSMC 130 nm LP - Memory optimized for high density and high speed - compiler range up to 64 k

Key Benefits

  • Smart periphery design to reach the highest density
  • Memory designed with SVT MOS for periphery and SVT
  • HD PRBC from TSMC for memory core
  • Flexible architecture
  • To offer several performance trade-offs for any memory
  • size
  • Multiple form factors proposed by the generator for a
  • given capacity
  • Variable write mask capability
  • Easy integration
  • Data range flexibility allows easy addition of bits for
  • redundancy or ECC purposes
  • Address range flexibility allows easy addition of single
  • rows for redundancy purposes
  • The Dolphin Integration quality
  • Complete mismatch validation of the memory architecture
  • taking into account local and global dispersion
  • Optional BIST for industrial fabrication test of instances
  • Compliance with TSMC IP 9000 qualification process


VT Bit cell
VT Periphery
Operating Voltage
Option mode
130 LP
SVT SVT Nominal voltage:
1.5 V +/-10%

Low voltage:

64k bits -