Dual Port SRAM compiler - TSMC 55 LPeF - Memory optimized for high density and low power - compiler range up to 32 k

• Reduce the die cost
• Unique architecture optimizing the periphery area for outstanding area gain
• Routing allowed upwards from Metal 4, Support Metal 5 top Metal option
• Extend the battery life
• Ultra low leakage thanks to careful design strcutures
• Optional bit wise write capability
• Data retention mode
• Make the integration easier
• Wide flexibility for words and bits per word
• Two completely independent Read/Write Ports which implements full Dual-Port (2RW) functionality
• Enable right on 1st pass design
• Complete mismatch validation of the memory architecture taking in account local and global dispersion
• Extended validation for high coverage rate of the compiler
• Decrease of Time-To-Market
• Multi foundries support using the same architecture