Metal programmable ROM compiler - TSMC 180 nm G - Non volatile memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k

Key Benefits

  • Ultra low dynamic power
  • Decrease of packaging cost
  • Smaller SoC area
  • 45% less consuming than conventional metal or via ROM at nominal voltage
  • Functionality down to 1.1 V +/-10%: 2.5 times less consuming compared to standard operation at 1.8 V
  • Decrease of fabrication costs
  • Metal 1 and Via metal 1-2 programmable ROM
  • Compatible with 1P4M SoC
  • Up to 20% denser than conventional metal or via ROM
  • Low leakage
  • No leakage in memory plane
  • Minimal leakage in memory periphery
  • Up to 3 times less leaky than conventional metal or via ROM
  • The Dolphin quality
  • Silicon Proven architecture
  • Vias half as numerous in comparison with a traditional metal or via ROM
  • CASSIOPEIA Architecture using bigger transistors for optimized read margin and low sensitivity to mismatch

Performances

Variants
VT Bit cell
VT Periphery
Operating Voltage
Capacity
Option mode
180 G
 Dolphin bit cell SVT Nominal voltage:
1.8 V +/-10%

Low voltage:
1.1 V +/-10%

 1 kbit to 1 Mbit -

Technical resources

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