Metal programmable ROM compiler - TSMC 152 nm LP - Non volatile memory optimized for low power and high density - compiler range up to 1024 k

• Ultra low dynamic power
• Decrease of packaging cost
• Smaller SoC area
• 45% less consuming than conventional metal or via ROM
• Decrease of fabrication costs
• Metal 1 and Via metal 1-2 programmable ROM
• Compatible with 1P4M SoC
• 20% denser than conventional metal or via ROM
• Low leakage
• No leakage in memory plane
• Minimal leakage in memory periphery
• 60% less leaky than conventional metal or via ROM
• Optimal DfY
• Vias half as numerous in comparison with a traditional metal or via ROM
• CASSIOPEIA Architecture using bigger transistors for optimized read margin and low sensitivity to mismatch