Foundry sponsored - Single Port SRAM compiler - TSMC 55 nm HV - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k

• Reach the highest density
• Thanks to smart periphery design
• using High density Pushed Rules Foundry bitcell
• use only 3 metal levels inside the memory
• Extend the battery life
• Designed with partitioned array to reach ultra low power consumption at 1.2 V
• Support stand by mode
• Make the integration easier
• MUX option enabling several performance tradeoffs and form factor
• Data range flexibility allows easy addition of bits for
• ECC purposes
• Address range flexibility allows easy addition of single rows for redundancy purposes
• Enable right on 1st pass design, the Dolphin integration quality
• Complete mismatch validation of the memory architecture taking in account local and global dispersion
• Extended validation for high coverage rate of the compiler
• Silicon proven per TSMC 9000 quality standard
• Decrease of Time-To-Market
• Multi foundries support using the same architecture