Key Benefits

  • Migration of an existing architecture already available for other processes (90, 85, 55 nm)
  • Smart periphery design to reach the highest density
  • Memory designed with SVT MOS for periphery and SVT uHD PRBC from TSMC for memory core
  • Ultra Low dynamic power
  • Partitioned array
  • Variable write-mask capability
  • Flexible power routing: power ring or ring-less
  • Low leakage design
  • Stand by mode
  • Data retention mode at 1.5 V to divide leakage by 25% compared to simple stand by mode
  • Easy integration
  • Data range flexibility allows easy addition of bits for redundancy or ECC purposes
  • Address range flexibility allows easy addition of single rows for redundancy purposes
  • The Dolphin quality
  • Complete mismatch validation of the memory architecture taking into account local and global dispersion
  • Optional BIST for industrial fabrication test of instances
  • Compliance with TSMC IP 9000 qualification process

Performances

Variants
VT Bit cell
VT Periphery
Operating Voltage
Capacity
Option mode
110 HV
- SVT Nominal voltage:
1.5 V +/- 10%

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