Single Port SRAM compiler - TSMC 55 nm LPeF - Memory optimized for high density and Low power - compiler range up to 320 k

Key Benefits

  • Configuration
  • SVT MOS for memory periphery
  • uHD HVT pushed rule bit-cell from foundry
  • Designed with 4 metal layers, routing enabled over the memory in metal 4 within free routing tracks
  • Migration on an existing architecture already available for other processes (90, 85, 55 nm)
  • Smart periphery design to reach the highest density
  • Up to 20% denser than standard memory generators at 55 nm
  • Ultra low leakage design
  • Data retention mode at nominal voltage (1.2 V) and low voltage (0.77 V): for 4x leakage reduction
  • Low dynamic power
  • Partitioned array
  • Variable write-mask capability
  • Easy integration
  • MUX options
  • Data range flexibility allows easy addition of bits for redundancy or ECC purposes
  • Address range flexibility allows easy addition of single rows for redundancy purposes
  • The Dolphin quality
  • Complete mismatch validation of the memory architecture taking in account local and global dispersion
  • Optional BIST for industrial fabrication test of instances


VT Bit cell
VT Periphery
Operating Voltage
Option mode
55 LP eFlash
- SVT Nominal voltage:
1.2 V +/-10%

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