Single Port SRAM compiler - TSMC 65 nm LP - Memory optimized for ultra high density and high speed - compiler range up to 320 k

• Configuration
• SVT MOS for memory periphery
• uHD HVT pushed rule bit-cell from foundry
• Smart periphery design to reach the highest density
• Up to 20% denser than standard memory generators
• Ultra low leakage design
• Up to 30% less leaky in retention mode compared with a standard offering at 65 nm LP
• Data retention mode at nominal voltage (1.2 V) and low voltage (0.77 V): for 4x leakage reduction
• Low dynamic power
• Partitioned array
• Variable write-mask capability
• Easy integration
• MUX options
• Data range flexibility allows easy addition of bits for redundancy or ECC purposes
• Address range flexibility allows easy addition of single rows for redundancy purposes
• The Dolphin quality
• Complete mismatch validation of the memory architecture taking in account local and global dispersion
• Optional BIST for industrial fabrication test of instances