Key Benefits

  • Available for Free Download and Use
  • Source biasing implementation for ultra low leakage
  • 4 times less leakage compared to stand by mode
  • 3 times less leakage compared to retention mode
  • Designed with the latest uLL PRBC from TSMC and a mix of HVT and SVT MOS
  • Low dynamic power
  • Low voltage capability: 30% power consumption savings when operating at 1.0 V +/-10%
  • Reduced die cost
  • Up to 10% denser than standard memory compilers available at 90 nm
  • Easy integration
  • MUX options
  • Data range flexibility allows easy addition of bits for redundancy or ECC purposes
  • Address range flexibility allows easy addition of single rows for redundancy purposes
  • Write mask
  • The Dolphin quality
  • Complete mismatch validation of the memory architecture taking in account local and global dispersion
  • Partitioned array for best low voltage performances
  • Sense amplifier optimized for low voltage operation
  • High robustness thanks to self-timing access scheme
  • Optional BIST for industrial fabrication test of instances
  • Compliance with TSMC IP 9000 qualification process

Performances

Variants
VT Bit cell
VT Periphery
Operating Voltage
Capacity
Option mode
90 uLL
uLL HVT
SVT
Nominal voltage:
1.2 V +/-10%

Low voltage:
1.0 V +/-10%

8 kbits to 640 kbits -