Key Benefits

  • Reduced die cost
  • Up to 10% denser than traditional memory compiler
  • uHD Pushed rule bit cell from foundry
  • Ultra low dynamic power
  • Low power architecture even at nominal voltage: Up to 50% less consuming than standard memory compilers available at 90 nm LP
  • Low voltage capability: 20% additional power consumption savings when operating at 1.0 V +/-10%
  • Byte write capability
  • Ultra low leakage design
  • Up to 25% less leaky in stand by mode compared with a standard offering at 90 nm LP
  • Memory designed with HVt MOS for periphery and HVt PRBC from TSMC for memory core
  • Optional Data retention mode (RHEA-RR option): only the memory plane and the circuitry for retention would remain powered. Note that this data-retention mode requires 2 VDD power supply lines and one GND
  • Easy integration
  • Mux factor can be chosen
  • Architecture specifically designed to limit dynamic IR Drop
  • Models of peak current delivered for free
  • The Dolphin quality
  • Complete mismatch validation of the memory architecture taking in account local and global dispersion
  • Partitioned array for best low voltage performances
  • Sense amplifier optimized for low voltage operation
  • High robustness thanks to self-timing access scheme
  • Optional BIST for industrial fabrication test of instances

Performances

Variants
VT Bit cell
VT Periphery
Operating Voltage
Capacity
Option mode
90 LP
- HVT Nominal voltage:
1.2 V +/-10%

Low voltage:
1.0 V +/-10%

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