Single Port SRAM compiler - TSMC 90 nm LPeF - Memory optimized for ultra low leakage (source biasing) and high density - compiler range up to 640 k

• Configuration
• SVT transistors for memory periphery
• uHD HVT Pushed rule bit cell from foundry
• Designed with 4 metal layers, routing enabled over the memory in metal 5
• Source biasing for ultra low leakage
• 4x leakage savings compared to standard stand by mode
• 30% leakage savings compared to standard retention mode without source biasing
• Smart periphery design to reach the highest density
• Up to 10% denser than standard memory generators at 90 nm
• Low dynamic power
• Partitioned array to reach ultra low power consumption
• Variable write-mask capability
• Easy integration
• MUX options
• Data range flexibility allows easy addition of bits for redundancy or ECC purposes
• Address range flexibility allows easy addition of single rows for redundancy purposes
• The Dolphin quality
• Complete mismatch validation of the memory architecture taking in account local and global dispersion
• High robustness thanks to self-timing access scheme