Foundry sponsored - Single Port SRAM compiler - TSMC 55 nm HV - Memory optimized for high density and Low power - compiler range up to 640 k

• Reach the highest density
• Thanks to smart periphery design
• Using High density Pushed Rules Foundry bitcell
• Extend the battery life
• Designed with partitioned array to reach ultra low power consumption at 1.2 V
• Support a couple of power saving modes: stand by and data retention mode
• Make the integration easier
• MUX option enabling several performance tradeoffs and form factor
• Data range flexibility allows easy addition of bits for
• ECC purposes
• Address range flexibility allows easy addition of single
• rows for redundancy purposes
• Enable right on 1st pass design, the integration quality
• Complete mismatch validation of the memory architecture taking in account local and global dispersion
• Extended validation for high coverage rate of the compiler
• Silicon proven per TSMC 9000 quality standard
• Decrease of Time-To-Market
• Multi foundries support using the same architecture