Key Benefits

  • Ultra-low-leakage even in a generic process
  • No leakage in memory plane
  • Minimal leakage in memory periphery while achieving between 230 and 300 MHz in worst case in TSMC 90 nm LP !
  • Key patent for high density with only one programming layer
  • Optimized for high DfY i.e. no compromise at the cost of design margins such as read margin

Performances

Variants
VT Bit cell
VT Periphery
Operating Voltage
Capacity
Option mode
90 LP
- SVT Nominal voltage:
1.2 V +/-10%

16kbits to 1Mbit -