Metal programmable ROM compiler - TSMC 90 nm LP - Non volatile memory optimized for low power - compiler range up to 1024 k
Key Benefits
- Ultra-low-leakage even in a generic process
- No leakage in memory plane
- Minimal leakage in memory periphery while achieving between 230 and 300 MHz in worst case in TSMC 90 nm LP !
- Key patent for high density with only one programming layer
- Optimized for high DfY i.e. no compromise at the cost of design margins such as read margin
Performances
Variants
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VT Bit cell
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VT Periphery
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Operating Voltage
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Capacity
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Option mode
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90 LP
|
- | SVT | Nominal voltage: 1.2 V +/-10% |
16kbits to 1Mbit | - |