Foundry sponsored - sROMet compiler - TSMC 55 nm uLP - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M

Key Benefits

  • REDUCE DIE COST
  • Via 1 programmable ROM
  • Key patent for high density with a single programming layer
  • Gain in density over alternative ROM designs
  • EXTEND BATTERY LIFE
  • Significant gain in dynamic power consumption compared to alternative ROM
  • No leakage in memory plane and minimal leakage in memory periphery
  • MAKE INTEGRATION EASIER
  • Depending on memory capacity. A large number of MUX options can be selected between 8 and 128
  • High flexibility for address range
  • ENABLE RIGHT ON FIRST PASS DESIGN
  • Complete mismatch validation of the memory architecture taking in account local and global dispersion

Performances

Variants
VT Bit cell
VT Periphery
Operating Voltage
Capacity
Option mode
55 uLP
 Dolphin bit cell SVT Nominal voltage:
1.1V +/-10% and 1.2V +/-10%

Low voltage:
0.9 V +/-10%

 512 bits - 0.5 Mbits -

Technical resources

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