Key Benefits

  • KEY FEATURES
  • Key patent "two in one" for ultra-high-density for large capacities starting at 1 Mbit
  • Ultra-low-leakage even in generic process:
  • no leakage in memory plane
  • minimal leakage in memory periphery
  • Optimized for high DfY i.e. no compromise at the cost of design margins such as read margin
  • Protection against piracy thanks to : patented bit cell and customized scrambling capabilities

Performances

Variants
VT Bit cell
VT Periphery
Operating Voltage
Capacity
Option mode
90 LP
- SVT Nominal voltage:
1.2 V +/-10%

196608x32m96 - 128kx32m64 - 160kx32m80 -