nLR-Charny-ref-[1.62-3.63]-[0.8-2.5]-Ixx.02, as any Power Management Virtual Component designed by Dolphin Design, is readily retargetable toward any submicron CMOS process.
Low noise: high power Supply Rejection Ratio (PSRR): - 65 dB at F < 10 kHz
Low intrinsic noise: 20 uVRMS at 10 Hz to 20 kHz
Low Bill-of-Material: optimized in density for the best trade-off for the given output current and input voltage range
Cost efficient solution compared to external Power Management.
Compatible with both Tantalum and ceramic capacitors
Behavioral models: ease integration in SoC and optimized Power Management Network (PMNet) by verifying mode transitions as well as noise propagation
Output current configuration
100 mA - 200 mA - 300 mA
AR - VR
3 % DC output voltage accuracy
- 60 dB PSRR
Different load current configuration: from 100 mA to 500 mA
20 uVRMS total integrated noise from 20 Hz to 20 kHz
Technology: TSMC 55 uLP
Over-voltage protection module (OPM) required for 2.7 to 5.5 V and 1.9 to 4.4 V input voltage range. The OPM enables over-voltage operation (up to 5.5 V) while using standard process 3.3 V devices.
Power-On-Reset and Brown-On-Reset circuit (POR-BOR)
Power ON indicator