Power Management Platform - SPIDER / Voltage Monitoring
Combined Power-On-Reset and Low-voltage detector designed in Samsung Foundries 65nm LFR6LP
Bias current reference are provided by capacitor-less low quiescent LDO designed in the same process node (see qLR-Della-cl-ref-[1.8-5.5]-[0.9-1.4].02 )
Low-voltage monitoring solution for power-critical IoT applications
The POR-LVD-[1.8-5.5]-[0.9-1.4].01 includes a Power-On-Reset used to monitor AVD and VDD supplies and to generate information to the SoC regarding the proper establishment of these AVD and VDD supplies.
The detection threshold for VDD is fixed while the threshold for AVD monitoring is programmable. For a SoC in an ultra-low power mode, the circuits allowing a programmable threshold monitoring of AVD can be de-activated to reduce current consumption.
Output current configuration
Monitored voltage range for AVD from 1.8 V to 5.5 V
The AVD monitoring threshold is programmable in normal operating mode
Monitored voltage range for VDD: from 0.9 V to 1.4 V
POR hysteresis: 100 mV
50 nA of operating current for POR function
200 nA of operating current for POR and LVD functions