R-Stratus-LPRR is an updated release of cache controller for MCU based on Non Volatile Memories (NVM) like eFlash or EEPROM. R-Stratus LPRR update consist in retainin the last 4x cache line accessed​ thus increasing the number of Hit 0 (get data from cache) ratio vs Hit 1 (read tag before getting data from cache)​. It provides the twofold advantage of speed improvement and of power consumption minimization. It is AMBA 3 AHB-lite compliant. R-Stratus LPRR includes a Retention Ready feature to allow fast CPU wake-up from deep sleep mode.

Key Benefits

  • TSMC Soft IP qualification (IP9000)
  • First cache controller optimized for low power
  • Performance optimization (optional)
  • Apparent frequency is accelerated up to 11 times
  • Zero wait state for cache hit
  • Architecture designed to minimize the number of accesses to TAG and cache RAM and NVM
  • Runtime programmable cache line size and associativity
  • Up to 14 times less power consuming!Support of AHB-Lite interfaces to ensure fast and smooth integration in any MCU subsystem without need for any bridge
  • External TAG and Cache memories to improve portability across a wide range of process technologies
  • Standard interface for TAG and Cache memories
  • Highly user configurable cache controller (associativity, cache line size, critical word first...) simplified with Smartvision for checking in simulation that the configuration is optimal for achieving the best speed and power consumption
  • Improvement of processing power
  • Critical word first to reduce the number of cycles in case of miss

Key Performances

  • Decreases the power consumption from 3 to 14 times, while increasing the average access time from 3 to 11 times
  • Decreases drastically the CPU boot time by 4 after deep sleep mode.