R-Stratus-LPRR is an updated release of cache controller for MCU based on Non Volatile Memories (NVM) like eFlash or EEPROM.
R-Stratus LPRR update consist in retainin the last 4x cache line accessed thus increasing the number of Hit 0 (get data from cache) ratio vs Hit 1 (read tag before getting data from cache). It provides the twofold advantage of speed improvement and of power consumption minimization. It is AMBA 3 AHB-lite compliant.
R-Stratus LPRR includes a Retention Ready feature to allow fast CPU wake-up from deep sleep mode.