Key Benefits

  • 1. Reduce the die cost
  • Unique architecture optimizing the periphery area for outstanding area gain
  • 2. Extend the battery life
  • Leakage reduction thanks to careful design structures,optional retention mode and choice of SVT/HVT periphery
  • Dynamic power reduction thanks to segment partitioning
  • Data retention mode at 1.2 V +/-10%, 1.1 V +/-10%, 0.9 V +/-10% and 0.6 V +/-10% to drastically divide the leakage compared to simple stand by mode
  • 3. Make the integration easier
  • Wide flexibility for words and bits per word
  • Two Read/Write Ports which implements full Two-Port (1R/1W) functionality
  • Flexible segment partitioning (Selectable 1-2 segments) allow the user to choose the best optimization between area, speed & power for his application
  • Embedded extinction&retention switchs (ERS optional)
  • 4. Enable right on 1st pass design, the Dolphin integration quality
  • Complete mismatch validation of the memory architecture taking in account local and global dispersion
  • Extended validation for high coverage rate of the compiler

Performances

Variants
VT Bit cell
VT Periphery
Operating Voltage
Capacity
Option mode
55 uLP
N/A HVT
SVT
Nominal voltage:
1.2 V +/-10%, 1.1 V +/-10%

Low voltage:
1.0 V +/-10%, 0.9 V +/-10%

16k -